7 citations · 12 across the 2 of their papers we have counts for
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cs.AR2022★ 5 cited
Low Error-Rate Approximate Multiplier Design for DNNs with Hardware-Driven Co-Optimization
Yao Lu, Jide Zhang, Su Zheng +2
In this paper, two approximate 3*3 multipliers are proposed and the synthesis results of the ASAP-7nm process library justify that they can reduce the area by 31.38% and 36.17%, an…
cs.AR2020
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations
SeyedRamin Rasoulinezhad, Siddhartha, Hao Zhou +3
We propose two tiers of modifications to FPGA logic cell architecture to deliver a variety of performance and utilization benefits with only minor area overheads. In the irst tier,…