activity
20182024
most citedA 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference

294 citations · 641 across the 22 of their papers we have counts for

collaborators

24 papers

cs.LG2024

On the Role of Noise in Factorizers for Disentangling Distributed Representations

Geethan Karunaratne, Michael Hersche, Abu Sebastian +1

To efficiently factorize high-dimensional distributed representations to the constituent atomic vectors, one can exploit the compute-in-superposition capabilities of vector-symboli…

cs.IR2024

Retro-li: Small-Scale Retrieval Augmented Generation Supporting Noisy Similarity Searches and Domain Shift Generalization

Gentiana Rashiti, Geethan Karunaratne, Mrinmaya Sachan +2

The retrieval augmented generation (RAG) system such as Retro has been shown to improve language modeling capabilities and reduce toxicity and hallucinations by retrieving from a d…

cs.CV2024

Zero-shot Classification using Hyperdimensional Computing

Samuele Ruffino, Geethan Karunaratne, Michael Hersche +3

Classification based on Zero-shot Learning (ZSL) is the ability of a model to classify inputs into novel classes on which the model has not previously seen any training examples. P…

cs.LG2023

TCNCA: Temporal Convolution Network with Chunked Attention for Scalable Sequence Processing

Aleksandar Terzic, Michael Hersche, Geethan Karunaratne +3

MEGA is a recent transformer-based architecture, which utilizes a linear recurrent operator whose parallel computation, based on the FFT, scales as , with being the s…

cs.LG2023★ 8 cited

MIMONets: Multiple-Input-Multiple-Output Neural Networks Exploiting Computation in Superposition

Nicolas Menet, Michael Hersche, Geethan Karunaratne +3

With the advent of deep learning, progressively larger neural networks have been designed to solve complex tasks. We take advantage of these capacity-rich models to lower the cost…

cs.CV2023

Factorizers for Distributed Sparse Block Codes

Michael Hersche, Aleksandar Terzic, Geethan Karunaratne +6

Distributed sparse block codes (SBCs) exhibit compact representations for encoding and manipulating symbolic data structures using fixed-width vectors. One major challenge however…

cs.DC2023★ 7 cited

WHYPE: A Scale-Out Architecture with Wireless Over-the-Air Majority for Scalable In-memory Hyperdimensional Computing

Robert Guirado, Abbas Rahimi, Geethan Karunaratne +3

Hyperdimensional computing (HDC) is an emerging computing paradigm that represents, manipulates, and communicates data using long random vectors known as hypervectors. Among differ…

cs.ET2022★ 294 cited

A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference

Manuel Le Gallo, Riduan Khaddam-Aljameh, Milos Stanisavljevic +26

The need to repeatedly shuttle around synaptic weight values from memory to processing units has been a key source of energy inefficiency associated with hardware implementation of…

cs.ET2022★ 31 cited

In-memory factorization of holographic perceptual representations

Jovin Langenegger, Geethan Karunaratne, Michael Hersche +3

Disentanglement of constituent factors of a sensory signal is central to perception and cognition and hence is a critical task for future artificial intelligence systems. In this p…

cs.LG2022★ 2 cited

In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory

Geethan Karunaratne, Michael Hersche, Jovin Langenegger +15

Continually learning new classes from a few training examples without forgetting previous old classes demands a flexible architecture with an inevitably growing portion of storage,…

cs.AR2022

Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference

Nazareno Bruschi, Giuseppe Tagliavini, Francesco Conti +7

Analog In-Memory Computing (AIMC) is emerging as a disruptive paradigm for heterogeneous computing, potentially delivering orders of magnitude better peak performance and efficienc…

cs.AR2022

Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing

Robert Guirado, Abbas Rahimi, Geethan Karunaratne +3

Hyperdimensional computing (HDC) is an emerging computing paradigm that represents, manipulates, and communicates data using very long random vectors (aka hypervectors). Among diff…

cs.CV2022

Constrained Few-shot Class-incremental Learning

Michael Hersche, Geethan Karunaratne, Giovanni Cherubini +3

Continually learning new classes from fresh data without forgetting previous knowledge of old classes is a very challenging research problem. Moreover, it is imperative that such l…

cs.LG2022★ 9 cited

Generalized Key-Value Memory to Flexibly Adjust Redundancy in Memory-Augmented Networks

Denis Kleyko, Geethan Karunaratne, Jan M. Rabaey +2

Memory-augmented neural networks enhance a neural network with an external key-value memory whose complexity is typically dominated by the number of support vectors in the key memo…

cs.AR2022★ 2 cited

A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks

Angelo Garofalo, Gianmarco Ottavi, Francesco Conti +4

Deployment of modern TinyML tasks on small battery-constrained IoT devices requires high computational energy efficiency. Analog In-Memory Computing (IMC) using non-volatile memory…

cs.AR2021★ 5 cited

End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet?

Gianmarco Ottavi, Geethan Karunaratne, Francesco Conti +3

In-Memory Acceleration (IMA) promises major efficiency improvements in deep neural network (DNN) inference, but challenges remain in the integration of IMA within a digital system.…

cs.ET2021★ 21 cited

Energy Efficient In-memory Hyperdimensional Encoding for Spatio-temporal Signal Processing

Geethan Karunaratne, Manuel Le Gallo, Michael Hersche +4

The emerging brain-inspired computing paradigm known as hyperdimensional computing (HDC) has been proven to provide a lightweight learning framework for various cognitive tasks com…

cs.ET2020★ 23 cited

Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors

Sergi Abadal, Robert Guirado, Hamidreza Taghvaee +18

The main design principles in computer architecture have recently shifted from a monolithic scaling-driven approach to the development of heterogeneous architectures that tightly c…

cs.ET2020★ 113 cited

Robust High-dimensional Memory-augmented Neural Networks

Geethan Karunaratne, Manuel Schmuck, Manuel Le Gallo +4

Traditional neural networks require enormous amounts of data to build their complex mappings during a slow training procedure that hinders their abilities for relearning and adapti…

eess.SP2020

ChewBaccaNN: A Flexible 223 TOPS/W BNN Accelerator

Renzo Andri, Geethan Karunaratne, Lukas Cavigelli +1

Binary Neural Networks enable smart IoT devices, as they significantly reduce the required memory footprint and computational complexity while retaining a high network performance…

cs.LG2020

ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning

Vinay Joshi, Geethan Karunaratne, Manuel Le Gallo +5

Deep neural networks (DNNs) have surpassed human-level accuracy in a variety of cognitive tasks but at the cost of significant memory/time requirements in DNN training. This limits…

cs.ET2020★ 122 cited

Mixed-precision deep learning based on computational memory

S. R. Nandakumar, Manuel Le Gallo, Christophe Piveteau +11

Deep neural networks (DNNs) have revolutionized the field of artificial intelligence and have achieved unprecedented success in cognitive tasks such as image and speech recognition…

cs.ET2019★ 1 cited

In-memory hyperdimensional computing

Geethan Karunaratne, Manuel Le Gallo, Giovanni Cherubini +3

Hyperdimensional computing (HDC) is an emerging computational framework that takes inspiration from attributes of neuronal circuits such as hyperdimensionality, fully distributed h…

cs.CV2018★ 3 cited

XNORBIN: A 95 TOp/s/W Hardware Accelerator for Binary Convolutional Neural Networks

Andrawes Al Bahou, Geethan Karunaratne, Renzo Andri +2

Deploying state-of-the-art CNNs requires power-hungry processors and off-chip memory. This precludes the implementation of CNNs in low-power embedded systems. Recent research shows…