23 citations · 52 across the 8 of their papers we have counts for
9 papers
Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems
Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi +1
The design space exploration of scaled-out manycores for communication-intensive applications (e.g., graph analytics and sparse linear algebra) is hampered due to either lack of sc…
Tascade: Hardware Support for Atomic-free, Asynchronous and Efficient Reduction Trees
Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff +1
Graph search and sparse data-structure traversal workloads contain challenging irregular memory patterns on global data structures that need to be modified atomically. Distributed…
DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications
Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi +1
In recent years, the growing demand to process large graphs and sparse datasets has led to increased research efforts to develop hardware- and software-based architectural solution…
Using LLMs to Facilitate Formal Verification of RTL
Marcelo Orenes-Vera, Margaret Martonosi, David Wentzlaff
Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as Sy…
Massive Data-Centric Parallelism in the Chiplet Era
Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff +1
Recent works have introduced task-based parallelization schemes to accelerate graph search and sparse data-structure traversal, where some solutions scale up to thousands of proces…
Wafer-Scale Fast Fourier Transforms
Marcelo Orenes-Vera, Ilya Sharapov, Robert Schreiber +3
We have implemented fast Fourier transforms for one, two, and three-dimensional arrays on the Cerebras CS-2, a system whose memory and processing elements reside on a single silico…
Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications
Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff +1
Applications with low data reuse and frequent irregular memory accesses, such as graph or sparse linear algebra workloads, fail to scale well due to memory bottlenecks and poor cor…
AutoSVA: Democratizing Formal Verification of RTL Module Interactions
Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff +1
Modern SoC design relies on the ability to separately verify IP blocks relative to their own specifications. Formal verification (FV) using SystemVerilog Assertions (SVA) is an eff…
The MosaicSim Simulator (Full Technical Report)
Opeoluwa Matthews, Aninda Manocha, Davide Giri +7
As Moore's Law has slowed and Dennard Scaling has ended, architects are increasingly turning to heterogeneous parallelism and domain-specific hardware-software co-designs. These tr…