2 papers
cs.AR2021
AutoSVA: Democratizing Formal Verification of RTL Module Interactions
Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff +1
Modern SoC design relies on the ability to separately verify IP blocks relative to their own specifications. Formal verification (FV) using SystemVerilog Assertions (SVA) is an eff…
cs.AR2020
The MosaicSim Simulator (Full Technical Report)
Opeoluwa Matthews, Aninda Manocha, Davide Giri +7
As Moore's Law has slowed and Dennard Scaling has ended, architects are increasingly turning to heterogeneous parallelism and domain-specific hardware-software co-designs. These tr…