57 citations · 108 across the 4 of their papers we have counts for
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cs.AR2026
Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
Sajjad Ahmed, Alexander Kropotov, Roberto Ignacio Genovese +21
The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, w…
cs.AR2021★ 57 cited
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures
Cristóbal Ramírez Lazo, César Alejandro Hernández, Oscar Palomar +3
Vector architectures lack tools for research. Consider the gem5 simulator, which is possibly the leading platform for computer-system architecture research. Unfortunately, gem5 doe…