57 citations · 108 across the 4 of their papers we have counts for
4 papers
Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
Sajjad Ahmed, Alexander Kropotov, Roberto Ignacio Genovese +21
The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, w…
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures
Cristóbal Ramírez Lazo, César Alejandro Hernández, Oscar Palomar +3
Vector architectures lack tools for research. Consider the gem5 simulator, which is possibly the leading platform for computer-system architecture research. Unfortunately, gem5 doe…
Proceedings of the Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2020)
Miquel Pericas, Oscar Palomar, Vassilis Papaefstathiou +1
This volume contains the proceedings of the 13th International Workshop on Programmability and Architectures for Heterogeneous Multicores. The workshop was held in conjunction with…
Navigating the Landscape for Real-time Localisation and Mapping for Robotics and Virtual and Augmented Reality
Sajad Saeedi, Bruno Bodin, Harry Wagstaff +23
Visual understanding of 3D environments in real-time, at low power, is a huge computational challenge. Often referred to as SLAM (Simultaneous Localisation and Mapping), it is cent…