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20192026
most citedPythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning

94 citations · 289 across the 24 of their papers we have counts for

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19 papers · 1 filter

cs.AR2026

CertiFlash: A Formal Verification Framework for Flash Translation Layers in Computational Solid State Drives

Harshita Gupta, Mayank Kabra, Rakesh Nadig +10

Data-intensive applications move large amounts of data from storage to the compute unit, incurring significant data movement overhead. Storage-centric computing reduces this overhe…

cs.AR2026

Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation

Konstantinos Kanellopoulos, Spiros Galanopoulos, Konstantinos Sgouras +7

Physical memory allocation establishes virtual-to-physical mappings on demand. In current systems, each minor page fault traps into the kernel and triggers pipeline flushes, stalls…

cs.AR2026★ 1 cited

Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning

Rahul Bera, Zhenrong Lang, Caroline Hengartner +4

Prefetching and off-chip prediction are two techniques proposed to hide long memory access latencies in high-performance processors. In this work, we demonstrate that: (1) prefetch…

cs.AR2025

Revelator: Rapid Data Fetching via System-Software-Guided Hash-based Speculative Address Translation

Konstantinos Kanellopoulos, Konstantinos Sgouras, Harsh Songara +7

Address translation is a major performance bottleneck in modern computing systems. Predicting the physical address (PA) of requested data before address translation completes can h…

cs.AR2025

SAGe: A Lightweight Algorithm-Architecture Co-Design for Mitigating the Data Preparation Bottleneck in Large-Scale Genome Sequence Analysis

Nika Mansouri Ghiasi, Talu Güloglu, Harun Mustafa +8

Genome sequence analysis, which examines the DNA sequences of organisms, drives advances in many critical medical and biotechnological fields. Given its importance and the exponent…

cs.AR2024

Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution

Rahul Bera, Adithya Ranganathan, Joydeep Rakshit +8

Load instructions often limit instruction-level parallelism (ILP) in modern processors due to data and resource dependences they cause. Prior techniques like Load Value Prediction…