124 citations · 414 across the 26 of their papers we have counts for
34 papers
Trail: Scalable and Low-Cost Temporal TLB Prefetching via Page-Table-Embedded Deltas
Konstantinos Kanellopoulos, Konstantinos Sgouras, Harsh Songara +2
Address translation is a major bottleneck in data-intensive workloads. TLB prefetching can hide translation latency, but existing spatial prefetchers struggle with irregular access…
Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
Harsh Songara, Konstantinos Kanellopoulos, F. Nisa Bostancı +6
DRAM continues to limit the performance, energy efficiency, and robustness of modern systems. Many prior works propose DRAM techniques that support in-DRAM computation, improve mem…
Argus: Agentic, Reference-Calibrated, Tree-Guided, System-Software-Level Bottleneck Localization
Vlad-Petru Nitu, Harsh Songara, Konstantinos Sgouras +3
Operating system (OS) code can account for a substantial share of CPU execution time. First, as application logic is offloaded to heterogeneous accelerators (e.g., GPUs), the CPU i…
CertiFlash: A Formal Verification Framework for Flash Translation Layers in Computational Solid State Drives
Harshita Gupta, Mayank Kabra, Rakesh Nadig +10
Data-intensive applications move large amounts of data from storage to the compute unit, incurring significant data movement overhead. Storage-centric computing reduces this overhe…
Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation
Konstantinos Kanellopoulos, Spiros Galanopoulos, Konstantinos Sgouras +7
Physical memory allocation establishes virtual-to-physical mappings on demand. In current systems, each minor page fault traps into the kernel and triggers pipeline flushes, stalls…
ColumnKeeper: Efficient Solutions to the ColumnDisturb Vulnerability in DRAM-based Systems
Andreas Kosmas Kakolyris, F. Nisa Bostanci, Ataberk Olgun +7
Modern DRAM chips are vulnerable to read disturbance phenomena such as RowHammer and RowPress, which induce bitflips after accessing nearby rows a certain number of times (the read…
HE-PIM: Demystifying Homomorphic Operations on a Real-world Processing-in-Memory System
Harshita Gupta, Mayank Kabra, Jaewoo Park +9
Homomorphic encryption (HE) enables computation over encrypted data, offering strong privacy guarantees for untrusted computing environments. Practical adoption remains limited by…
Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning
Rahul Bera, Zhenrong Lang, Caroline Hengartner +4
Prefetching and off-chip prediction are two techniques proposed to hide long memory access latencies in high-performance processors. In this work, we demonstrate that: (1) prefetch…
Revelator: Rapid Data Fetching via System-Software-Guided Hash-based Speculative Address Translation
Konstantinos Kanellopoulos, Konstantinos Sgouras, Harsh Songara +7
Address translation is a major performance bottleneck in modern computing systems. Predicting the physical address (PA) of requested data before address translation completes can h…
SAGe: A Lightweight Algorithm-Architecture Co-Design for Mitigating the Data Preparation Bottleneck in Large-Scale Genome Sequence Analysis
Nika Mansouri Ghiasi, Talu Güloglu, Harun Mustafa +8
Genome sequence analysis, which examines the DNA sequences of organisms, drives advances in many critical medical and biotechnological fields. Given its importance and the exponent…
Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses
F. Nisa Bostancı, Oğuzhan Canpolat, Ataberk Olgun +5
DRAM chips are vulnerable to read disturbance phenomena (e.g., RowHammer and RowPress), where repeatedly accessing or keeping open a DRAM row causes bitflips in nearby rows. Attack…
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution
Rahul Bera, Adithya Ranganathan, Joydeep Rakshit +8
Load instructions often limit instruction-level parallelism (ILP) in modern processors due to data and resource dependences they cause. Prior techniques like Load Value Prediction…
BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads
Oğuzhan Canpolat, A. Giray Yağlıkçı, Ataberk Olgun +5
RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in other physically nearby DRAM rows.…
Revisiting Main Memory-Based Covert and Side Channel Attacks in the Context of Processing-in-Memory
F. Nisa Bostanci, Konstantinos Kanellopoulos, Ataberk Olgun +6
We introduce IMPACT, a set of high-throughput main memory-based timing attacks that leverage characteristics of processing-in-memory (PiM) architectures to establish covert and sid…
Virtuoso: Enabling Fast and Accurate Virtual Memory Research via an Imitation-based Operating System Simulation Methodology
Konstantinos Kanellopoulos, Konstantinos Sgouras, F. Nisa Bostanci +7
The unprecedented growth in data demand from emerging applications has turned virtual memory (VM) into a major performance bottleneck. Researchers explore new hardware/OS co-design…
CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost
F. Nisa Bostanci, Ismail Emir Yuksel, Ataberk Olgun +5
We propose a new RowHammer mitigation mechanism, CoMeT, that prevents RowHammer bitflips with low area, performance, and energy costs in DRAM-based systems at very low RowHammer th…
Evaluating Homomorphic Operations on a Real-World Processing-In-Memory System
Harshita Gupta, Mayank Kabra, Juan Gómez-Luna +2
Computing on encrypted data is a promising approach to reduce data security and privacy risks, with homomorphic encryption serving as a facilitator in achieving this goal. In this…
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources
Konstantinos Kanellopoulos, Hong Chul Nam, F. Nisa Bostanci +5
Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks…
ALP: Alleviating CPU-Memory Data Movement Overheads in Memory-Centric Systems
Nika Mansouri Ghiasi, Nandita Vijaykumar, Geraldo F. Oliveira +7
Partitioning applications between NDP and host CPU cores causes inter-segment data movement overhead, which is caused by moving data generated from one segment (e.g., instructions,…
Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings
Konstantinos Kanellopoulos, Rahul Bera, Kosta Stojiljkovic +8
Conventional virtual memory (VM) frameworks enable a virtual address to flexibly map to any physical address. This flexibility necessitates large data structures to store virtual-t…
RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory
Nika Mansouri Ghiasi, Mohammad Sadrosadati, Geraldo F. Oliveira +9
Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip, allowing for fine-grained connections between la…
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction
Rahul Bera, Konstantinos Kanellopoulos, Shankar Balachandran +4
Long-latency load requests continue to limit the performance of high-performance processors. To increase the latency tolerance of a processor, architects have primarily relied on t…
PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques
Ataberk Olgun, Juan Gomez Luna, Konstantinos Kanellopoulos +4
DRAM-based main memory is used in nearly all computing systems as a major component. One way of overcoming the main memory bottleneck is to move computation near memory, a paradigm…
SeGraM: A Universal Hardware Accelerator for Genomic Sequence-to-Graph and Sequence-to-Sequence Mapping
Damla Senol Cali, Konstantinos Kanellopoulos, Joel Lindegger +15
A critical step of genome sequence analysis is the mapping of sequenced DNA fragments (i.e., reads) collected from an individual to a known linear reference genome sequence (i.e.,…