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researcher

G. Yeric

4 papers hereh-index 182k citations61 works total

Matching runs newest-first, so older work may not be attached to this profile yet.

author position
  • middle author2
  • last author2

Across the 4 of 4 papers where every author was matched, so the position is known.

fields
  • cs.AR2
  • cond-mat.mes-hall1
  • cs.ET1

identity via Semantic Scholar / OpenAlex

activity
20182022
most citedStandard Cell Library Design and Optimization Methodology for ASAP7 PDK

11 citations · 29 across the 4 of their papers we have counts for

collaborators
Showing cs.ETShow all

1 paper · 1 filter

cs.ET2021

Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor

Chi-Shuen Lee, Brian Cline, Saurabh Sinha +2

We present a DevIce-to-System Performance EvaLuation (DISPEL) workflow that integrates transistor and interconnect modeling, parasitic extraction, standard cell library characteriz…

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Not affiliated with arXiv. Researcher data from Semantic Scholar (ODC-BY) and OpenAlex.