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researcher

G. Yeric

4 papers hereh-index 182k citations61 works total

Matching runs newest-first, so older work may not be attached to this profile yet.

author position
  • middle author2
  • last author2

Across the 4 of 4 papers where every author was matched, so the position is known.

fields
  • cs.AR2
  • cond-mat.mes-hall1
  • cs.ET1

identity via Semantic Scholar / OpenAlex

activity
20182022
most citedStandard Cell Library Design and Optimization Methodology for ASAP7 PDK

11 citations · 29 across the 4 of their papers we have counts for

collaborators
Showing cs.ARShow all

2 papers · 1 filter

cs.AR2020★ 10 cited

Stack up your chips: Betting on 3D integration to augment Moore's Law scaling

Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava +3

3D integration, i.e., stacking of integrated circuit layers using parallel or sequential processing is gaining rapid industry adoption with the slowdown of Moore's law scaling. 3D…

cs.AR2018★ 11 cited

Standard Cell Library Design and Optimization Methodology for ASAP7 PDK

Xiaoqing Xu, Nishi Shah, Andrew Evans +3

Standard cell libraries are the foundation for the entire backend design and optimization flow in modern application-specific integrated circuit designs. At 7nm technology node and…

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Not affiliated with arXiv. Researcher data from Semantic Scholar (ODC-BY) and OpenAlex.