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cs.LG2026
SwiftCTS: Fast Cross-Design Prediction and Pareto Optimization of Clock Tree Metrics via Few-Shot Calibration
Barsat Khadka, Kawsher Roxy, Md Rubel Ahmed
Clock Tree Synthesis (CTS) is a computationally expensive stage in the physical design flow, requiring iterative EDA tool invocations to navigate a vast configuration space for opt…
cs.LG2026
CTS-Bench: Benchmarking Graph Coarsening Trade-offs for GNNs in Clock Tree Synthesis
Barsat Khadka, Kawsher Roxy, Md Rubel Ahmed
Graph Neural Networks (GNNs) are increasingly explored for physical design analysis in Electronic Design Automation, particularly for modeling Clock Tree Synthesis behavior such as…
cs.LG2022
Deep Bidirectional Transformers for SoC Flow Specification Mining
Md Rubel Ahmed, Hao Zheng
High-quality system-level message flow specifications can lead to comprehensive validation of system-on-chip (SoC) designs. We propose a disruptive method that utilizes an attentio…