3 citations · 6 across the 8 of their papers we have counts for
9 papers
SwiftCTS: Fast Cross-Design Prediction and Pareto Optimization of Clock Tree Metrics via Few-Shot Calibration
Barsat Khadka, Kawsher Roxy, Md Rubel Ahmed
Clock Tree Synthesis (CTS) is a computationally expensive stage in the physical design flow, requiring iterative EDA tool invocations to navigate a vast configuration space for opt…
CTS-Bench: Benchmarking Graph Coarsening Trade-offs for GNNs in Clock Tree Synthesis
Barsat Khadka, Kawsher Roxy, Md Rubel Ahmed
Graph Neural Networks (GNNs) are increasingly explored for physical design analysis in Electronic Design Automation, particularly for modeling Clock Tree Synthesis behavior such as…
EdgeProfiler: A Fast Profiling Framework for Lightweight LLMs on Edge Using Analytical Model
Alyssa Pinnock, Shakya Jayakody, Kawsher A Roxy +1
This paper introduces EdgeProfiler, a fast profiling framework designed for evaluating lightweight Large Language Models (LLMs) on edge systems. While LLMs offer remarkable capabil…
AutoModel: Automatic Synthesis of Models from Communication Traces of SoC Designs
Md Rubel Ahmed, Bardia Nadimi, Hao Zheng
Modeling system-level behaviors of intricate System-on-Chip (SoC) designs is crucial for design analysis, testing, and validation. However, the complexity and volume of SoC traces…
Mining SoC Message Flows with Attention Model
Md Rubel Ahmed, Bardia Nadimi, Hao Zheng
High-quality system-level message flow specifications are necessary for comprehensive validation of system-on-chip (SoC) designs. However, manual development and maintenance of suc…
Deep Bidirectional Transformers for SoC Flow Specification Mining
Md Rubel Ahmed, Hao Zheng
High-quality system-level message flow specifications can lead to comprehensive validation of system-on-chip (SoC) designs. We propose a disruptive method that utilizes an attentio…
Tools and Algorithms for SoC Communication Traces
Md Rubel Ahmed, Hao Zheng
In this paper, we study seven well-known trace analysis techniques both from the hardware and software domain and discuss their performance on communication-centric system-on-chip…
Model Synthesis for Communication Traces of System-on-Chip Designs
Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee +2
Concise and abstract models of system-level behaviors are invaluable in design analysis, testing, and validation. In this paper, we consider the problem of inferring models from co…
Mining Message Flows from System-on-Chip Execution Traces
MD Rubel Ahmed, Hao Zheng, Parijat Mukherjee +2
Comprehensive and well-defined specifications are necessary to perform rigorous and thorough validation of system-on-chip (SoC) designs. Message flows specify how components of an…