49 citations · 123 across the 21 of their papers we have counts for
24 papers
SensWear: An Open, Modular, and AI-Ready Wearable Platform
Dariush Salami, Behzad Salami, Huseyin Yigitler
Wearable AI/ML research needs raw, synchronized, and reconfigurable multimodal data, but consumer devices are closed and many research platforms remain tied to one embodiment or se…
A Generic Modulo- RNS Multiplier Based on Twit Representation
Saeid Gorgin, Amirhossein Sadr, Behzad Salami +1
Modular multiplication is a fundamental arithmetic primitive in Residue Number Systems (RNS) and is often the dominant source of delay, area, and energy consumption in RNS datapath…
REPTILES: Repeated Tiles of Sargantana, a RISC-V multicore based on OpenPiton
Noelia Oliete-Escuín, Arnau Bigas, Narcís Rodas +26
Chip industry continues advancing and expanding modern computing systems, resulting in more complex multi-core processors. Conversely, academic projects face scalability challenges…
Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
Sajjad Ahmed, Alexander Kropotov, Roberto Ignacio Genovese +21
The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, w…
EMiX: Emulating Beyond Single-FPGA Limits
Alexander Kropotov, Miquel Moreto, Behzad Salami
FPGA-level emulation is a key step in pre-silicon chip design validation. However, emulating large-scale multi-core systems increasingly exceed the hardware resource capacity of a…
Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs
Elias Perdomo, Alexander Kropotov, Francelly Cano +4
Emulating chip functionality before silicon production is crucial, especially with the increasing prevalence of RISC-V-based designs. FPGAs are promising candidates for such purpos…
Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips
Ataberk Olgun, Majd Osseiran, Abdullah Giray Yaglikci +6
We experimentally demonstrate the effects of read disturbance (RowHammer and RowPress) and uncover the inner workings of undocumented read disturbance defense mechanisms in High Ba…
An Experimental Analysis of RowHammer in HBM2 DRAM Chips
Ataberk Olgun, Majd Osseiran, Abdullah Giray Ya{ğ}lık{c}ı +6
RowHammer (RH) is a significant and worsening security, safety, and reliability issue of modern DRAM chips that can be exploited to break memory isolation. Therefore, it is importa…
TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs
İsmail Emir Yüksel, Ataberk Olgun, Behzad Salami +6
Prior works propose SRAM-based TRNGs that extract entropy from SRAM arrays. SRAM arrays are widely used in a majority of specialized or general-purpose chips that perform the compu…
NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Accelerators
Aditya Manglik, Minesh Patel, Haiyu Mao +4
Resistive Random-Access Memory (RRAM) is well-suited to accelerate neural network (NN) workloads as RRAM-based Processing-in-Memory (PIM) architectures natively support highly-para…
PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques
Ataberk Olgun, Juan Gomez Luna, Konstantinos Kanellopoulos +4
DRAM-based main memory is used in nearly all computing systems as a major component. One way of overcoming the main memory bottleneck is to move computation near memory, a paradigm…
PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM
Ataberk Olgun, Juan Gómez Luna, Konstantinos Kanellopoulos +4
Processing-using-memory (PuM) techniques leverage the analog operation of memory cells to perform computation. Several recent works have demonstrated PuM techniques in off-the-shel…
MoRS: An Approximate Fault Modelling Framework for Reduced-Voltage SRAMs
İsmail Emir Yüksel, Behzad Salami, Oğuz Ergin +2
On-chip memory (usually based on Static RAMs-SRAMs) are crucial components for various computing devices including heterogeneous devices, e.g., GPUs, FPGAs, ASICs to achieve high p…
On the Impact of Device-Level Techniques on Energy-Efficiency of Neural Network Accelerators
Seyed Morteza Nabavinejad, Behzad Salami
Energy-efficiency is a key concern for neural network applications. To alleviate this issue, hardware acceleration using FPGAs or GPUs can provide better energy-efficiency than gen…
Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage Underscaling
Seyed Saber Nabavi Larimi, Behzad Salami, Osman S. Unsal +3
Modern computing devices employ High-Bandwidth Memory (HBM) to meet their memory bandwidth requirements. An HBM-enabled device consists of multiple DRAM layers stacked on top of on…
Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware Margins
George Papadimitriou, Athanasios Chatzidimitriou, Dimitris Gizopoulos +5
Modern large-scale computing systems (data centers, supercomputers, cloud and edge setups and high-end cyber-physical systems) employ heterogeneous architectures that consist of mu…
Power and Accuracy of Multi-Layer Perceptrons (MLPs) under Reduced-voltage FPGA BRAMs Operation
Behzad Salami, Osman Unsal, Adrian Cristal
In this paper, we exploit the aggressive supply voltage underscaling technique in Block RAMs (BRAMs) of Field Programmable Gate Arrays (FPGAs) to improve the energy efficiency of M…
An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration
Behzad Salami, Erhan Baturay Onural, Ismail Emir Yuksel +6
We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Ne…
On the Resilience of Deep Learning for Reduced-voltage FPGAs
Kamyar Givaki, Behzad Salami, Reza Hojabr +6
Deep Neural Networks (DNNs) are inherently computation-intensive and also power-hungry. Hardware accelerators such as Field Programmable Gate Arrays (FPGAs) are a promising solutio…
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing
B. Salami, K. Parasyris, A. Cristal +42
The LEGaTO project leverages task-based programming models to provide a software ecosystem for Made in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engi…
A Novel FPGA-Based High Throughput Accelerator For Binary Search Trees
Oyku Melikoglu, Oguz Ergin, Behzad Salami +3
This paper presents a deeply pipelined and massively parallel Binary Search Tree (BST) accelerator for Field Programmable Gate Arrays (FPGAs). Our design relies on the extremely pa…
Hardware Versus Software Fault Injection of Modern Undervolted SRAMs
Muhammet Abdullah Soyturk, Konstantinos Parasyris, Behzad Salami +3
To improve power efficiency, researchers are experimenting with dynamically adjusting the supply voltage of systems below the nominal operating points. However, production systems…
Evaluating Built-in ECC of FPGA on-chip Memories for the Mitigation of Undervolting Faults
Behzad Salami, Osman S. Unsal, Adrian Cristal Kestelman
Voltage underscaling below the nominal level is an effective solution for improving energy efficiency in digital circuits, e.g., Field Programmable Gate Arrays (FPGAs). However, fu…
On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation
Behzad Salami, Osman Unsal, Adrian Cristal
Machine Learning (ML) is making a strong resurgence in tune with the massive generation of unstructured data which in turn requires massive computational resources. Due to the inhe…