1 citations · 2 across the 3 of their papers we have counts for
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Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores
Rakesh Kumar, Mehdi Alipour, David Black-Schaffer
Exploiting memory level parallelism (MLP) is crucial to hide long memory and last level cache access latencies. While out-of-order (OoO) cores, and techniques building on them, are…
A Variable Vector Length SIMD Architecture for HW/SW Co-designed Processors
Rakesh Kumar, Alejandro Martinez, Antonio Gonzalez
Hardware/Software (HW/SW) co-designed processors provide a promising solution to the power and complexity problems of the modern microprocessors by keeping their hardware simple. M…
Fetch-Directed Instruction Prefetching Revisited
Truls Asheim, Rakesh Kumar, Boris Grot
Prior work has observed that fetch-directed prefetching (FDIP) is highly effective at covering instruction cache misses. The key to FDIP's effectiveness is having a sufficiently la…