1 citations · 2 across the 4 of their papers we have counts for
4 papers
Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores
Rakesh Kumar, Mehdi Alipour, David Black-Schaffer
Exploiting memory level parallelism (MLP) is crucial to hide long memory and last level cache access latencies. While out-of-order (OoO) cores, and techniques building on them, are…
A Variable Vector Length SIMD Architecture for HW/SW Co-designed Processors
Rakesh Kumar, Alejandro Martinez, Antonio Gonzalez
Hardware/Software (HW/SW) co-designed processors provide a promising solution to the power and complexity problems of the modern microprocessors by keeping their hardware simple. M…
Fetch-Directed Instruction Prefetching Revisited
Truls Asheim, Rakesh Kumar, Boris Grot
Prior work has observed that fetch-directed prefetching (FDIP) is highly effective at covering instruction cache misses. The key to FDIP's effectiveness is having a sufficiently la…
Network Coding for Critical Infrastructure Networks
Rakesh Kumar, Vignesh Babu, David M. Nicol
The applications in the critical infrastructure systems pose simultaneous resilience and performance requirements to the underlying computer network. To meet such requirements, the…