34 citations · 42 across the 5 of their papers we have counts for
5 papers
AnySyn: A Cost-Generic Logic Synthesis Framework with Customizable Cost Functions
Hanyu Wang, Siang-Yun Lee, Giovanni De Micheli
Modern technology-independent logic synthesis has been developed to optimize for the size and depth of AND-Inverter Graphs (AIGs) as a proxy of CMOS circuit area and delay. However…
An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications
Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
Correctness and robustness are essential for logic synthesis applications, but they are often only tested with a limited set of benchmarks. Moreover, when the application fails on…
Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits
Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
The adiabatic quantum-flux parametron (AQFP) is a promising energy-efficient superconducting technology. Before technology mapping, additional buffer and splitter cells need to be…
Simulation-Guided Boolean Resubstitution
Siang-Yun Lee, Heinz Riener, Alan Mishchenko +2
This paper proposes a new logic optimization paradigm based on circuit simulation, which reduces the need for Boolean computations such as SAT-solving or constructing BDDs. The pap…
The EPFL Logic Synthesis Libraries
Mathias Soeken, Heinz Riener, Winston Haaswijk +8
We present a collection of modular open source C++ libraries for the development of logic synthesis applications. These libraries can be used to develop applications for the design…