43 citations · 70 across the 6 of their papers we have counts for
6 papers
Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation
Zhiyao Xie, Rongjian Liang, Xiaoqing Xu +3
Net length is a key proxy metric for optimizing timing and power across various stages of a standard digital design flow. However, the bulk of net length information is not availab…
Fast IR Drop Estimation with Machine Learning
Zhiyao Xie, Hai Li, Xiaoqing Xu +2
IR drop constraint is a fundamental requirement enforced in almost all chip designs. However, its evaluation takes a long time, and mitigation techniques for fixing violations may…
Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology
Rahul Mathur, Chien-Ju Chao, Rossana Liu +6
3D integration technologies are seeing widespread adoption in the semiconductor industry to offset the limitations and slowdown of two-dimensional scaling. High-density 3D integrat…
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling
Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava +3
3D integration, i.e., stacking of integrated circuit layers using parallel or sequential processing is gaining rapid industry adoption with the slowdown of Moore's law scaling. 3D…
Standard Cell Library Design and Optimization Methodology for ASAP7 PDK
Xiaoqing Xu, Nishi Shah, Andrew Evans +3
Standard cell libraries are the foundation for the entire backend design and optimization flow in modern application-specific integrated circuit designs. At 7nm technology node and…
Methodology for standard cell compliance and detailed placement for triple patterning lithography
Bei Yu, Xiaoqing Xu, Jhih-Rong Gao +1
As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography…