42 citations · 202 across the 30 of their papers we have counts for
16 papers · 1 filter
HYDRA: A Heterogeneous Chiplet DSE Framework for Serving Dynamic Hybrid LLM Workloads
Jiahao Lin, Alish Kanani, Sangwan Lee +2
Hybrid Transformer-Mamba large language models (LLMs) enhance long-context efficiency, but their heterogeneous computation and communication patterns complicate efficient hardware…
APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inference
Alish Kanani, Layan Badawi, Umit Y. Ogras
Mixture-of-Experts (MoE) models are attractive for edge deployment because they provide high model capacity while activating only a small subset of parameters per token, improving…
Uni-SFU: Algorithm-HW Co-Design for Universal SFUs via Mixed-Degree Piecewise Approximation
Miao Sun, Yucheng Huang, Mingcong Cao +3
Nonlinear activation functions are essential to modern deep neural networks (DNNs), but their hardware evaluation places significant pressure on the special-function units (SFUs) o…
ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.5D PIM Chiplet Architectures
Vibhanshu Sharma, Alish Kanani, Miao Sun +3
Processing-in-memory (PIM)-based 2.5D multi-chiplet platforms are enablers for machine learning (ML) workloads. However, their performance is affected by the power delivery network…
CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems
Lukas Pfromm, Alish Kanani, Harsh Sharma +3
Due to reduced manufacturing yields, traditional monolithic chips cannot keep up with the compute, memory, and communication demands of data-intensive applications, such as rapidly…
THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures
Alish Kanani, Lukas Pfromm, Harsh Sharma +3
Chiplet-based integration enables large-scale systems that combine diverse technologies, enabling higher yield, lower costs, and scalability, making them well-suited to AI workload…
Designing High-Performance and Thermally Feasible Multi-Chiplet Architectures enabled by Non-bendable Glass Interposer
Harsh Sharma, Janardhan Rao Doppa, Umit Y. Ogras +1
Multi-chiplet architectures enabled by glass interposer offer superior electrical performance, enable higher bus widths due to reduced crosstalk, and have lower capacitance in the…
MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures
Lukas Pfromm, Alish Kanani, Harsh Sharma +6
Rapidly evolving artificial intelligence and machine learning applications require ever-increasing computational capabilities, while monolithic 2D design technologies approach thei…
A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models
Harsh Sharma, Pratyush Dhingra, Janardhan Rao Doppa +2
Transformers have revolutionized deep learning and generative modeling, enabling advancements in natural language processing tasks. However, the size of transformer models is incre…
COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks
Sumit K. Mandal, Gokul Krishnan, A. Alper Goksoy +3
Graph convolutional networks (GCNs) have shown remarkable learning capabilities when processing graph-structured data found inherently in many application areas. GCNs distribute th…
DAS: Dynamic Adaptive Scheduling for Energy-Efficient Heterogeneous SoCs
A. Alper Goksoy, Anish Krishnakumar, Md Sahil Hassan +4
Domain-specific systems-on-chip (DSSoCs) aim at bridging the gap between application-specific integrated circuits (ASICs) and general-purpose processors. Traditional operating syst…
Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks
Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti +3
With the widespread use of Deep Neural Networks (DNNs), machine learning algorithms have evolved in two diverse directions -- one with ever-increasing connection density for better…
Runtime Task Scheduling using Imitation Learning for Heterogeneous Many-Core Systems
Anish Krishnakumar, Samet E. Arda, A. Alper Goksoy +4
Domain-specific systems-on-chip, a class of heterogeneous many-core systems, are recognized as a key approach to narrow down the performance and energy-efficiency gap between custo…
DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework
Samet E. Arda, Anish NK, A. Alper Goksoy +6
Heterogeneous systems-on-chip (SoCs) are highly favorable computing platforms due to their superior performance and energy efficiency potential compared to homogeneous architecture…
Work-in-Progress: A Simulation Framework for Domain-Specific System-on-Chips
Samet E. Arda, Anish NK, A. Alper Goksoy +6
Heterogeneous system-on-chips (SoCs) have become the standard embedded computing platforms due to their potential to deliver superior performance and energy efficiency compared to…
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach
Umit Y. Ogras, Radu Marculescu
In this paper, we present a methodology for customized communication architecture synthesis that matches the communication requirements of the target application. This is an import…