203 citations · 677 across the 32 of their papers we have counts for
3 papers · 2 filters
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
Jason Blocklove, Shailja Thakur, Benjamin Tan +3
Traditionally, digital hardware designs are written in the Verilog hardware description language (HDL) and debugged manually by engineers. This can be time-consuming and error-pron…
Evaluating LLMs for Hardware Design and Test
Jason Blocklove, Siddharth Garg, Ramesh Karri +1
Large Language Models (LLMs) have demonstrated capabilities for producing code in Hardware Description Languages (HDLs). However, most of the focus remains on their abilities to wr…
LLM-aided explanations of EDA synthesis errors
Siyu Qiu, Benjamin Tan, Hammond Pearce
Training new engineers in digital design is a challenge, particularly when it comes to teaching the complex electronic design automation (EDA) tooling used in this domain. Learners…