75 citations · 80 across the 6 of their papers we have counts for
7 papers
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU
Geonhwa Jeong, Eric Qin, Ananda Samajdar +4
As AI-based applications become pervasive, CPU vendors are starting to incorporate matrix engines within the datapath to boost efficiency. Systolic arrays have been the premier arc…
Page Table Management for Heterogeneous Memory Systems
Sandeep Kumar, Aravinda Prasad, Smruti R. Sarangi +1
Modern enterprise servers are increasingly embracing tiered memory systems with a combination of low latency DRAMs and large capacity but high latency non-volatile main memories (N…
Proximu$: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute
Anant V. Nori, Rahul Bera, Shankar Balachandran +5
Deep Neural Network (DNN) inference is emerging as the fundamental bedrock for a multitude of utilities and services. CPUs continue to scale up their raw compute capabilities for D…
AccSS3D: Accelerator for Spatially Sparse 3D DNNs
Om Ji Omer, Prashant Laddha, Gurpreet S Kalsi +6
Semantic understanding and completion of real world scenes is a foundational primitive of 3D Visual perception widely used in high-level applications such as robotics, medical imag…
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis
Damla Senol Cali, Gurpreet S. Kalsi, Zülal Bingöl +13
Genome sequence analysis has enabled significant advancements in medical and scientific areas such as personalized medicine, outbreak tracing, and the understanding of evolution. U…
DSPatch: Dual Spatial Pattern Prefetcher
Rahul Bera, Anant V. Nori, Onur Mutlu +1
High main memory latency continues to limit performance of modern high-performance out-of-order cores. While DRAM latency has remained nearly the same over many generations, DRAM b…