81 citations · 118 across the 10 of their papers we have counts for
7 papers · 1 filter
GenPairX: A Hardware-Algorithm Co-Designed Accelerator for Paired-End Read Mapping
Julien Eudine, Chu Li, Zhuo Cheng +11
Genome sequencing has become a central focus in computational biology. A genome study typically begins with sequencing, which produces millions to billions of short DNA fragments k…
SAGe: A Lightweight Algorithm-Architecture Co-Design for Mitigating the Data Preparation Bottleneck in Large-Scale Genome Sequence Analysis
Nika Mansouri Ghiasi, Talu Güloglu, Harun Mustafa +8
Genome sequence analysis, which examines the DNA sequences of organisms, drives advances in many critical medical and biotechnological fields. Given its importance and the exponent…
MetaStore: High-Performance Metagenomic Analysis via In-Storage Computing
Nika Mansouri Ghiasi, Mohammad Sadrosadati, Harun Mustafa +9
Metagenomics has led to significant advancements in many fields. Metagenomic analysis commonly involves the key tasks of determining the species present in a sample and their relat…
TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs
İsmail Emir Yüksel, Ataberk Olgun, Behzad Salami +6
Prior works propose SRAM-based TRNGs that extract entropy from SRAM arrays. SRAM arrays are widely used in a majority of specialized or general-purpose chips that perform the compu…
Scrooge: A Fast and Memory-Frugal Genomic Sequence Aligner for CPUs, GPUs, and ASICs
Joël Lindegger, Damla Senol Cali, Mohammed Alser +3
Pairwise sequence alignment is a very time-consuming step in common bioinformatics pipelines. Speeding up this step requires heuristics, efficient implementations, and/or hardware…
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations
Lois Orosa, Yaohua Wang, Mohammad Sadrosadati +10
DRAM is the dominant main memory technology used in modern computing systems. Computing systems implement a memory controller that interfaces with DRAM via DRAM commands. DRAM exec…
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching
Yaohua Wang, Lois Orosa, Xiangjun Peng +8
DRAM Main memory is a performance bottleneck for many applications due to the high access latency. In-DRAM caches work to mitigate this latency by augmenting regular-latency DRAM w…