18 citations · 107 across the 18 of their papers we have counts for
6 papers · 1 filter
QTIA, a 2.5 or 10 Gbps 4-Channel Array Optical Receiver ASIC in a 65 nm CMOS Technology
H. Sun, X. Huang, C. -P. Chao +14
The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2…
A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip
H. Sun, Q. Sun, S. Biereigel +14
We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version…
The TaichuPix1: A Monolithic Active Pixel Sensor with fast in-pixel readout electronics for the CEPC vertex detector
T. Wu, S. Grinstein, R. Casanova +14
The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of high resolution, low material, fast readout and low power. The Mo…
In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip
H. Sun, D. Gong, C. Edwards +10
We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The…
Characterization and quality control test of a gigabit cable receiver ASIC (GBCR2) for the ATLAS Inner Tracker Detector upgrade
W. Zhang, C. Chen, D. Gong +10
We present the characterization and quality control test of a gigabit cable receiver ASIC prototype, GBCR2, for the ATLAS Inner Tracker pixel detector upgrade. GBCR2 equalizes and…
Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection
H. Sun, D. Gong, W. Zhang +10
We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge inj…