activity
20132024
most citedA Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade

23 citations · 253 across the 53 of their papers we have counts for

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Showing 2023Show all

6 papers · 1 filter

physics.ins-det2023

Performance of a front-end prototype ASIC for the ATLAS High Granularity Timing Detector

C. Agapopoulou, L. A. Beresford, D. E. Boumediene +34

This paper presents the design and characterisation of a front-end prototype ASIC for the ATLAS High Granularity Timing Detector, which is planned for the High-Luminosity phase of…

physics.ins-det2023★ 3 cited

MUX64, an analogue 64-to-1 multiplexer ASIC for the ATLAS High Granularity Timing Detector

Zifeng Xu, Li Zhang, Xing Huang +11

We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inp…

physics.ins-det2023★ 4 cited

GBT20, a 20.48 Gbps PAM4 Optical Transmitter Module for Particle Physics Experiments

B. Deng, L. Zhang, C. -P. Chao +14

We present a pluggable radiation-tolerant 4-level Pulse-Amplitude-Modulation (PAM4) optical transmitter module called GBT20 (Giga-Bit Transmitter at 20 Gbps) for particle-physics e…

physics.ins-det2023★ 2 cited

An FPGA-based readout chip emulator for the CMS ETL detector upgrade

L. Zhang, C. Edwards, D. Gong +9

We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digi…

physics.ins-det2023

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

L. Zhang, D. Gong, T. Liu +12

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototype…

physics.ins-det2023

A High-resolution Clock Phase Shifter Circuitry for ALTIROC

X. Huang, C. de La Taille, D. Gong +6

A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase…