47 citations · 58 across the 9 of their papers we have counts for
7 papers · 1 filter
Characterizing a Neutron-Induced Fault Model for Deep Neural Networks
Fernando Fernandes dos Santos, Angeliki Kritikakou, Josie Esteban Rodriguez Condia +4
The reliability evaluation of Deep Neural Networks (DNNs) executed on Graphic Processing Units (GPUs) is a challenging problem since the hardware architecture is highly complex and…
Comparing different solutions for testing resistive defects in low-power SRAMs
Nunzio Mirabella, Michelangelo Grosso, Giovanna Franchino +4
Low-power SRAM architectures are especially sensitive to many types of defects that may occur during manufacturing. Among these, resistive defects can appear. This paper analyzes s…
A Novel Compaction Approach for SBST Test Programs
Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
In-field test of processor-based devices is a must when considering safety-critical systems (e.g., in robotics, aerospace, and automotive applications). During in-field testing, di…
Exploring the Mysteries of System-Level Test
Ilia Polian, Jens Anders, Steffen Becker +7
System-level test, or SLT, is an increasingly important process step in today's integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in op…
New categories of Safe Faults in a processor-based Embedded System
C. C. Gursoy, M. Jenihhin, A. S. Oyeniran +4
The identification of safe faults (i.e., faults which are guaranteed not to produce any failure) in an electronic system is a crucial step when analyzing its dependability and its…
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
P. Bernardi, G. Masera, F. Quaglio +1
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-a-chip (SoC) environments. The approach advantages are the ab…
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
F. Lima Kastensmidt, L. Sterpone, L. Carro +1
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by…