17 citations · 89 across the 31 of their papers we have counts for
16 papers · 1 filter
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators
Mahdi Taheri, Natalia Cherezova, Mohammad Saeed Ansari +4
The stringent requirements for the Deep Neural Networks (DNNs) accelerator's reliability stand along with the need for reducing the computational burden on the hardware platforms,…
On-Chip Sensors Data Collection and Analysis for SoC Health Management
Konstantin Shibin, Maksim Jenihhin, Artur Jutman +2
Data produced by on-chip sensors in modern SoCs contains a large amount of information such as occurring faults, aging status, accumulated radiation dose, performance characteristi…
A Novel Fault-Tolerant Logic Style with Self-Checking Capability
Mahdi Taheri, Saeideh Sheikhpour, Ali Mahani +1
We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level. The proposed logic cells have two-rail inputs/outputs, and the functi…
Holistic IJTAG-based External and Internal Fault Monitoring in UAVs
Foisal Ahmed, Maksim Jenihhin
Cyber-Physical Systems (CPSs), such as Unmanned Aerial Vehicles (UAVs), use System-on-Chip (SoC) based computing platforms to perform multiple complex tasks in safety-critical appl…
Unsupervised Recycled FPGA Detection Using Symmetry Analysis
Tanvir Ahmad Tarique, Foisal Ahmed, Maksim Jenihhin +1
Recently, recycled field-programmable gate arrays (FPGAs) pose a significant hardware security problem due to the proliferation of the semiconductor supply chain. Ring oscillator (…
On BTI Aging Rejuvenation in Memory Address Decoders
Cemil Cem Gursoy, Daniel Kraak, Foisal Ahmed +3
Memory designs require timing margins to compensate for aging and fabrication process variations. With technology downscaling, aging mechanisms became more apparent, and larger mar…
Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects
Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux +2
Rapidly shrinking technology node and voltage scaling increase the susceptibility of Soft Errors in digital circuits. Soft Errors are radiation-induced effects while the radiation…
The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications
Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux +2
As an alternative to traditional fault injection-based methodologies and to explore the applicability of modern machine learning algorithms in the field of reliability engineering,…
Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors
Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux +2
The paper is proposing a methodology for modeling a gate-level netlist using a Graph Convolutional Network (GCN). The model predicts the overall functional de-rating factors of seq…
Representing Gate-Level SET Faults by Multiple SEU Faults at RTL
Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar +1
The advanced complex electronic systems increasingly demand safer and more secure hardware parts. Correspondingly, fault injection became a major verification milestone for both sa…
New categories of Safe Faults in a processor-based Embedded System
C. C. Gursoy, M. Jenihhin, A. S. Oyeniran +4
The identification of safe faults (i.e., faults which are guaranteed not to produce any failure) in an electronic system is a crucial step when analyzing its dependability and its…
Efficient Fault Injection based on Dynamic HDL Slicing Technique
Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik +1
This work proposes a fault injection methodology where Hardware Description Language (HDL) code slicing is exploited to prune fault injection locations, thus enabling more efficien…
Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing
Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik +1
Along with the complexity of electronic systems for safety-critical applications, the cost of safety mechanisms evaluation by fault injection simulation is rapidly going up. To red…
High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin +2
Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and functional safety of th…
Towards Multidimensional Verification: Where Functional Meets Non-Functional
Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri +1
Trends in advanced electronic systems' design have a notable impact on design verification technologies. The recent paradigms of Internet-of-Things (IoT) and Cyber-Physical Systems…
Mixed-level identification of fault redundancy in microprocessors
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin +2
A new high-level implementation independent functional fault model for control faults in microprocessors is introduced. The fault model is based on the instruction set, and is spec…