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X. Huang

3 papers here

Matching runs newest-first, so older work may not be attached to this profile yet.

author position
  • first author1
  • middle author1

Across the 2 of 3 papers where every author was matched, so the position is known.

fields
  • physics.ins-det3
ORCID 0000-0002-8654-8469
same name
  • X. Huang — 205 papers, h 74
  • X. Huang — 85 papers, h 29
  • X. Huang — 44 papers, h 48
  • X. Huang — 11 papers, h 30
  • X. Huang — 11 papers, h 46
  • X. Huang — 10 papers

Either other researchers who publish under this name, or the same person where the external sources have not merged their records.

identity via Semantic Scholar / OpenAlex

most citedMUX64, an analogue 64-to-1 multiplexer ASIC for the ATLAS High Granularity Timing Detector

3 citations · 5 across the 3 of their papers we have counts for

collaborators

3 papers

physics.ins-det2023★ 3 cited

MUX64, an analogue 64-to-1 multiplexer ASIC for the ATLAS High Granularity Timing Detector

Zifeng Xu, Li Zhang, Xing Huang +11

We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inp…

physics.ins-det2023★ 2 cited

An FPGA-based readout chip emulator for the CMS ETL detector upgrade

L. Zhang, C. Edwards, D. Gong +9

We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digi…

physics.ins-det2023

A High-resolution Clock Phase Shifter Circuitry for ALTIROC

X. Huang, C. de La Taille, D. Gong +6

A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase…

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Not affiliated with arXiv. Researcher data from Semantic Scholar (ODC-BY) and OpenAlex.