From the 1 of 5 linked papers with an AI index.
5 papers
Optimizing CMOS-compatible, superconducting titanium nitride resonators: Deposition conditions and structuring processes
Simon J. K. Lang, Alexandra Schewski, Ignaz Eisele +10
The paper investigates how deposition conditions, etching power, and resist‑strip temperature influence the performance of superconducting titanium nitride coplanar waveguide reson…
CMOS-compatible processing and room-temperature characterization on wafer-level for scalable quantum computing
S. J. K. Lang, T. Mayer, J. Weber +10
We report on an industry-grade CMOS-compatible qubit fabrication approach using a CMOS pilot line, enabling a yield of functional devices reaching 92.8 %, with a resistance spread…
3D-Integrated Superconducting qubits: CMOS-Compatible, Wafer-Scale Processing for Flip-Chip Architectures
T. Mayer, H. Bender, S. J. K. Lang +16
In this article, we present a technology development of a superconducting qubit device 3D-integrated by flip-chip-bonding and processed following CMOS fabrication standards and con…
CMOS-Compatible, Wafer-Scale Processed Superconducting Qubits Exceeding Energy Relaxation Times of 200us
T. Mayer, J. Weber, E. Music +12
We present the results of an industry-grade fabrication of superconducting qubits on 200 mm wafers utilizing CMOS-established processing methods. By automated waferprober resistanc…
Wafer-Scale Characterization of Al/AlxOy/Al Josephson Junctions at Room Temperature
Simon J. K. Lang, Ignaz Eisele, Johannes Weber +13
Josephson junctions (JJs) are the key element of many devices operating at cryogenic temperatures. Development of time-efficient wafer-scale JJ characterization for process optimiz…