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From the 3 of 6 linked papers with an AI index.

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6 papers

quant-ph2026

Optimizing CMOS-compatible, superconducting titanium nitride resonators: Deposition conditions and structuring processes

Simon J. K. Lang, Alexandra Schewski, Ignaz Eisele +10

The paper investigates how deposition conditions, etching power, and resist‑strip temperature influence the performance of superconducting titanium nitride coplanar waveguide reson…

quant-ph2026

Surface Optimization of Superconducting Aluminum Resonators for Robust Quantum Device Fabrication

Simon J. K. Lang, Ignaz Eisele, Alwin Maiwald +8

The paper studies surface treatment methods for aluminum superconducting resonators to maintain low dielectric loss after a 24‑hour ambient exposure, finding that selective oxide r…

quant-ph2026

Stability studies on subtractively-fabricated CMOS-compatible superconducting transmon qubits

Chawki Dhieb, Johannes Weber, Samuel Taubenberger +12

Developing fault-tolerant quantum processors with error correction demands large arrays of physical qubits whose key performance metrics (coherence times, control fidelities) must…

quant-ph2025

CMOS-compatible processing and room-temperature characterization on wafer-level for scalable quantum computing

S. J. K. Lang, T. Mayer, J. Weber +10

We report on an industry-grade CMOS-compatible qubit fabrication approach using a CMOS pilot line, enabling a yield of functional devices reaching 92.8 %, with a resistance spread…

quant-ph2025

3D-Integrated Superconducting qubits: CMOS-Compatible, Wafer-Scale Processing for Flip-Chip Architectures

T. Mayer, H. Bender, S. J. K. Lang +16

In this article, we present a technology development of a superconducting qubit device 3D-integrated by flip-chip-bonding and processed following CMOS fabrication standards and con…

quant-ph2025

CMOS-Compatible, Wafer-Scale Processed Superconducting Qubits Exceeding Energy Relaxation Times of 200us

T. Mayer, J. Weber, E. Music +12

We present the results of an industry-grade fabrication of superconducting qubits on 200 mm wafers utilizing CMOS-established processing methods. By automated waferprober resistanc…