120 citations · 162 across the 10 of their papers we have counts for
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cs.AR2023
Automatic multi-dimensional pipelining for high-level synthesis of dataflow accelerators
Kingshuk Majumder, Uday Bondhugula
In recent years, there has been a surging demand for edge computing of image processing and machine learning workloads. This has reignited interest in the development of custom har…
cs.AR2021★ 3 cited
HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description
Kingshuk Majumder, Uday Bondhugula
The emergence of machine learning, image and audio processing on edge devices has motivated research towards power efficient custom hardware accelerators. Though FPGAs are an ideal…
cs.AR2018
Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths
Vinamra Benara, Ziaul Choudhury, Suresh Purini +1
High-level synthesis (HLS) has received significant attention in recent years, improving programmability for FPGAs. PolyMage is a domain-specific language (DSL) for image processin…