120 citations · 162 across the 10 of their papers we have counts for
10 papers
PolyBlocks: A Compiler Infrastructure for AI Chips and Programming Frameworks
Uday Bondhugula, Akshay Baviskar, Navdeep Katel +3
We present the design and implementation of PolyBlocks, a modular and reusable MLIR-based compiler infrastructure for AI programming frameworks and AI chips. PolyBlocks is based on…
Automatic multi-dimensional pipelining for high-level synthesis of dataflow accelerators
Kingshuk Majumder, Uday Bondhugula
In recent years, there has been a surging demand for edge computing of image processing and machine learning workloads. This has reignited interest in the development of custom har…
High Performance GPU Code Generation for Matrix-Matrix Multiplication using MLIR: Some Early Results
Navdeep Katel, Vivek Khandelwal, Uday Bondhugula
This report presents some early results on code generation targeting tensor cores on NVIDIA GPUs using the MLIR compiler infrastructure. The state-of-the-art in high-performance de…
HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description
Kingshuk Majumder, Uday Bondhugula
The emergence of machine learning, image and audio processing on edge devices has motivated research towards power efficient custom hardware accelerators. Though FPGAs are an ideal…
High Performance Code Generation in MLIR: An Early Case Study with GEMM
Uday Bondhugula
This article is primarily meant to present an early case study on using MLIR, a new compiler intermediate representation infrastructure, for high-performance code generation. Aspec…
MLIR: A Compiler Infrastructure for the End of Moore's Law
Chris Lattner, Mehdi Amini, Uday Bondhugula +7
This work presents MLIR, a novel approach to building reusable and extensible compiler infrastructure. MLIR aims to address software fragmentation, improve compilation for heteroge…
A flexible FPGA accelerator for convolutional neural networks
Kingshuk Majumder, Shubham Nema, Uday Bondhugula
Though CNNs are highly parallel workloads, in the absence of efficient on-chip memory reuse techniques, an accelerator for them quickly becomes memory bound. In this paper, we prop…
Optimizing the Linear Fascicle Evaluation Algorithm for Multi-Core and Many-Core Systems
Karan Aggarwal, Uday Bondhugula
Sparse matrix-vector multiplication (SpMV) operations are commonly used in various scientific applications. The performance of the SpMV operation often depends on exploiting regula…
An Approach for Finding Permutations Quickly: Fusion and Dimension matching
Aravind Acharya, Uday Bondhugula, Albert Cohen
Polyhedral compilers can perform complex loop optimizations that improve parallelism and cache behaviour of loops in the input program. These transformations result in significant…
Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths
Vinamra Benara, Ziaul Choudhury, Suresh Purini +1
High-level synthesis (HLS) has received significant attention in recent years, improving programmability for FPGAs. PolyMage is a domain-specific language (DSL) for image processin…