81 citations · 250 across the 20 of their papers we have counts for
22 papers
An Experimental Analysis of RowHammer in HBM2 DRAM Chips
Ataberk Olgun, Majd Osseiran, Abdullah Giray Ya{ğ}lık{c}ı +6
RowHammer (RH) is a significant and worsening security, safety, and reliability issue of modern DRAM chips that can be exploited to break memory isolation. Therefore, it is importa…
Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud
Geraldo F. Oliveira, Juan Gómez-Luna, Saugata Ghose +2
Neural networks (NNs) are growing in importance and complexity. A neural network's performance (and energy efficiency) can be bound either by computation or memory resources. The p…
Going From Molecules to Genomic Variations to Scientific Discovery: Intelligent Algorithms and Architectures for Intelligent Genome Analysis
Mohammed Alser, Joel Lindegger, Can Firtina +5
We now need more than ever to make genome analysis more intelligent. We need to read, analyze, and interpret our genomes not only quickly, but also accurately and efficiently enoug…
High-throughput Pairwise Alignment with the Wavefront Algorithm using Processing-in-Memory
Safaa Diab, Amir Nassereldine, Mohammed Alser +3
We show that the wavefront algorithm can achieve higher pairwise read alignment throughput on a UPMEM PIM system than on a server-grade multi-threaded CPU system.
EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators
Lois Orosa, Skanda Koppula, Yaman Umuroglu +5
Dilated and transposed convolutions are widely used in modern convolutional neural networks (CNNs). These kernels are used extensively during CNN training and inference of applicat…
A Compiler Framework for Optimizing Dynamic Parallelism on GPUs
Mhd Ghaith Olabi, Juan Gómez Luna, Onur Mutlu +2
Dynamic parallelism on GPUs allows GPU threads to dynamically launch other GPU threads. It is useful in applications with nested parallelism, particularly where the amount of neste…
Extending Memory Capacity in Consumer Devices with Emerging Non-Volatile Memory: An Experimental Study
Geraldo F. Oliveira, Saugata Ghose, Juan Gómez-Luna +8
The number and diversity of consumer devices are growing rapidly, alongside their target applications' memory consumption. Unfortunately, DRAM scalability is becoming a limiting fa…
FPGA-Based Near-Memory Acceleration of Modern Data-Intensive Applications
Gagandeep Singh, Mohammed Alser, Damla Senol Cali +4
Modern data-intensive applications demand high computation capabilities with strict power constraints. Unfortunately, such applications suffer from a significant waste of both exec…
IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors
Jawad Haj-Yahya, Jeremie S. Kim, A. Giray Yaglikci +5
To operate efficiently across a wide range of workloads with varying power requirements, a modern processor applies different current management mechanisms, which briefly throttle…
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
Geraldo F. Oliveira, Juan Gómez-Luna, Lois Orosa +5
Data movement between the CPU and main memory is a first-order obstacle against improving performance, scalability, and energy efficiency in modern systems. Computer systems employ…
BurstLink: Techniques for Energy-Efficient Conventional and Virtual Reality Video Display
Jawad Haj-Yahya, Jisung Park, Rahul Bera +5
Conventional planar video streaming is the most popular application in mobile systems and the rapid growth of 360 video content and virtual reality (VR) devices are accelerating th…
SIMDRAM: A Framework for Bit-Serial SIMD Processing Using DRAM
Nastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio +7
Processing-using-DRAM has been proposed for a limited set of basic operations (i.e., logic operations, addition). However, in order to enable the full adoption of processing-using-…
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching
Yaohua Wang, Lois Orosa, Xiangjun Peng +8
DRAM Main memory is a performance bottleneck for many applications due to the high access latency. In-DRAM caches work to mitigate this latency by augmenting regular-latency DRAM w…
NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling
Gagandeep Singh, Dionysios Diamantopoulos, Christoph Hagleitner +4
Ongoing climate change calls for fast and accurate weather and climate modeling. However, when solving large-scale weather prediction simulations, state-of-the-art CPU and GPU impl…
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis
Damla Senol Cali, Gurpreet S. Kalsi, Zülal Bingöl +13
Genome sequence analysis has enabled significant advancements in medical and scientific areas such as personalized medicine, outbreak tracing, and the understanding of evolution. U…
SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations
Konstantinos Kanellopoulos, Nandita Vijaykumar, Christina Giannoula +6
Important workloads, such as machine learning and graph analytics applications, heavily involve sparse linear algebra operations. These operations use sparse matrix compression as…
SneakySnake: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs
Mohammed Alser, Taha Shahroodi, Juan Gomez-Luna +2
Motivation: We introduce SneakySnake, a highly parallel and highly accurate pre-alignment filter that remarkably reduces the need for computationally costly sequence alignment. The…
A Workload and Programming Ease Driven Perspective of Processing-in-Memory
Saugata Ghose, Amirali Boroumand, Jeremie S. Kim +2
Many modern and emerging applications must process increasingly large volumes of data. Unfortunately, prevalent computing paradigms are not designed to efficiently handle such larg…
Enabling Practical Processing in and near Memory for Data-Intensive Computing
Onur Mutlu, Saugata Ghose, Juan Gómez-Luna +1
Modern computing systems suffer from the dichotomy between computation on one side, which is performed only in the processor (and accelerators), and data storage/movement on the ot…
Processing Data Where It Makes Sense: Enabling In-Memory Computation
Onur Mutlu, Saugata Ghose, Juan Gómez-Luna +1
Today's systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in systems that cause performance, scala…
Enabling Efficient RDMA-based Synchronous Mirroring of Persistent Memory Transactions
Arash Tavakkol, Aasheesh Kolli, Stanko Novakovic +10
Synchronous Mirroring (SM) is a standard approach to building highly-available and fault-tolerant enterprise storage systems. SM ensures strong data consistency by maintaining mult…
Improving tasks throughput on accelerators using OpenCL command concurrency
A. J. Lázaro-Muñoz, J. M. González-Linares, J. Gómez-Luna +1
A heterogeneous architecture composed by a host and an accelerator must frequently deal with situations where several independent tasks are available to be offloaded onto the accel…