8 citations · 9 across the 10 of their papers we have counts for
6 papers · 1 filter
eIQ Neutron: Redefining Edge-AI Inference with Integrated NPU and Compiler Innovations
Lennart Bamberg, Filippo Minnella, Roberto Bosio +5
Neural Processing Units (NPUs) are key to enabling efficient AI inference in resource-constrained edge environments. While peak tera operations per second (TOPS) is often used to g…
VUSA: Virtually Upscaled Systolic Array Architecture to Exploit Unstructured Sparsity in AI Acceleration
Shereef Helal, Alberto Garcia-Ortiz, Lennart Bamberg
Leveraging high degrees of unstructured sparsity is a promising approach to enhance the efficiency of deep neural network DNN accelerators - particularly important for emerging Edg…
Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators
Lennart Bamberg, Arash Pourtaherian, Luc Waeijen +2
Manufacturing-viable neuromorphic chips require novel computer architectures to achieve the massively parallel and efficient information processing the brain supports so effortless…
Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs
Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar +4
We introduce ratatoskr, an open-source framework for in-depth power, performance and area (PPA) analysis in NoCs for 3D-integrated and heterogeneous System-on-Chips (SoCs). It cove…
System-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips
Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg +2
For a system-level design of Networks-on-Chip for 3D heterogeneous System-on-Chip (SoC), the locations of components, routers and vertical links are determined from an application…
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures
Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel +4
Heterogeneous 3D System-on-Chips (3D SoCs) are the most promising design paradigm to combine sensing and computing within a single chip. A special characteristic of communication n…