8 citations · 9 across the 10 of their papers we have counts for
10 papers
Rescaling-Aware Training for Efficient Deployment of Deep Learning Models on Full-Integer Hardware
Lion Mueller, Alberto Garcia-Ortiz, Ardalan Najafi +2
Integer AI inference significantly reduces computational complexity in embedded systems. Quantization-aware training (QAT) helps mitigate accuracy degradation associated with post-…
eIQ Neutron: Redefining Edge-AI Inference with Integrated NPU and Compiler Innovations
Lennart Bamberg, Filippo Minnella, Roberto Bosio +5
Neural Processing Units (NPUs) are key to enabling efficient AI inference in resource-constrained edge environments. While peak tera operations per second (TOPS) is often used to g…
VUSA: Virtually Upscaled Systolic Array Architecture to Exploit Unstructured Sparsity in AI Acceleration
Shereef Helal, Alberto Garcia-Ortiz, Lennart Bamberg
Leveraging high degrees of unstructured sparsity is a promising approach to enhance the efficiency of deep neural network DNN accelerators - particularly important for emerging Edg…
Exploiting Neural-Network Statistics for Low-Power DNN Inference
Lennart Bamberg, Ardalan Najafi, Alberto Garcia-Ortiz
Specialized compute blocks have been developed for efficient DNN execution. However, due to the vast amount of data and parameter movements, the interconnects and on-chip memories…
Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators
Lennart Bamberg, Arash Pourtaherian, Luc Waeijen +2
Manufacturing-viable neuromorphic chips require novel computer architectures to achieve the massively parallel and efficient information processing the brain supports so effortless…
Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs
Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar +4
We introduce ratatoskr, an open-source framework for in-depth power, performance and area (PPA) analysis in NoCs for 3D-integrated and heterogeneous System-on-Chips (SoCs). It cove…
System-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips
Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg +2
For a system-level design of Networks-on-Chip for 3D heterogeneous System-on-Chip (SoC), the locations of components, routers and vertical links are determined from an application…
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures
Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel +4
Heterogeneous 3D System-on-Chips (3D SoCs) are the most promising design paradigm to combine sensing and computing within a single chip. A special characteristic of communication n…
Simulation Environment for Link Energy Estimation in Networks-on-Chip with Virtual Channels
Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar +3
Network-on-chip (NoC) is the most promising design paradigm for the interconnect architecture of a multiprocessor system-on-chip (MPSoC). On the downside, a NoC has a significant i…
Area Optimization with Non-linear Models in Core Mapping for System-on-Chips
Jan Moritz Joseph, Dominik Ermel, Tobias Drewes +3
Linear models are regularly used for mapping cores to tiles in a chip. System-on-Chip (SoC) design requires integration of functional units with varying sizes, but conventional mod…