5 citations · 9 across the 6 of their papers we have counts for
7 papers
Super Efficient Neural Network for Compression Artifacts Reduction and Super Resolution
Wen Ma, Qiuwen Lou, Arman Kazemi +2
Video quality can suffer from limited internet speed while being streamed by users. Compression artifacts start to appear when the bitrate decreases to match the available bandwidt…
Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories
Mohammad Mehdi Sharifi, Lillian Pentecost, Ramin Rajaei +8
The memory wall bottleneck is a key challenge across many data-intensive applications. Multi-level FeFET-based embedded non-volatile memories are a promising solution for denser an…
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
Weiwen Jiang, Qiuwen Lou, Zheyu Yan +4
Co-exploration of neural architectures and hardware design is promising to simultaneously optimize network accuracy and hardware efficiency. However, state-of-the-art neural archit…
Nonvolatile Spintronic Memory Cells for Neural Networks
Andrew W. Stephan, Qiuwen Lou, Michael Niemier +2
A new spintronic nonvolatile memory cell analogous to 1T DRAM with non-destructive read is proposed. The cells can be used as neural computing units. A dual-circuit neural network…
Application-level Studies of Cellular Neural Network-based Hardware Accelerators
Qiuwen Lou, Indranil Palit, Tang Li +3
As cost and performance benefits associated with Moore's Law scaling slow, researchers are studying alternative architectures (e.g., based on analog and/or spiking circuits) and/or…
A mixed signal architecture for convolutional neural networks
Qiuwen Lou, Chenyun Pan, John McGuiness +4
Deep neural network (DNN) accelerators with improved energy and delay are desirable for meeting the requirements of hardware targeted for IoT and edge computing systems. Convolutio…
Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA
Junsong Wang, Qiuwen Lou, Xiaofan Zhang +3
Neural network accelerators with low latency and low energy consumption are desirable for edge computing. To create such accelerators, we propose a design flow for accelerating the…