22 citations · 113 across the 46 of their papers we have counts for
13 papers · 1 filter
Layer-wise Weight Selection for Power-Efficient Neural Network Acceleration
Jiaxun Fang, Grace Li Zhang, Shaoyi Huang
Systolic array accelerators execute CNNs with energy dominated by the switching activity of multiply accumulate (MAC) units. Although prior work exploits weight dependent MAC power…
CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference
Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann +1
Large Language Models (LLMs) have demonstrated remarkable potential in hardware front-end design using hardware description languages (HDLs). However, their inherent tendency towar…
VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning
Zhuorui Zhao, Bing Li, Grace Li Zhang +1
Large Language Models (LLMs) have shown impressive potential in generating Verilog codes, but ensuring functional correctness remains a challenge. Existing approaches often rely on…
SVG360: Editable Multiview Vector Graphics from a Single SVG
Mengnan Jiang, Zhaolin Sun, Christian Franke +3
Scalable Vector Graphics are a standard representation for editable visual design, yet they are usually authored as single view two dimensional illustrations. This limits their use…
Towards Fast LLM Fine-tuning through Zeroth-Order Optimization with Projected Gradient-Aligned Perturbations
Zhendong Mi, Qitao Tan, Grace Li Zhang +3
Fine-tuning large language models (LLMs) using zeroth-order (ZO) optimization has emerged as a promising alternative to traditional gradient-based methods due to its reduced memory…
Layer-wise dynamic rank for compressing large language models
Zhendong Mi, Bian Sun, Grace Li Zhang +1
Large language models (LLMs) have rapidly scaled in size, bringing severe memory and computational challenges that hinder their deployment. Singular Value Decomposition (SVD)-based…
LLM-NAS: LLM-driven Hardware-Aware Neural Architecture Search
Hengyi Zhu, Grace Li Zhang, Shaoyi Huang
Hardware-Aware Neural Architecture Search (HW-NAS) requires joint optimization of accuracy and latency under device constraints. Traditional supernet-based methods require multiple…
Revolution or Hype? Seeking the Limits of Large Models in Hardware Design
Qiang Xu, Leon Stok, Rolf Drechsler +3
Recent breakthroughs in Large Language Models (LLMs) and Large Circuit Models (LCMs) have sparked excitement across the electronic design automation (EDA) community, promising a re…
CompressKV: Semantic Retrieval Heads Know What Tokens are Not Important Before Generation
Xiaolin Lin, Jingcun Wang, Olga Kondrateva +3
Recent advances in large language models (LLMs) have significantly boosted long-context processing. However, the increasing key-value (KV) cache size poses critical challenges to m…
Deep Joint Source-Channel Coding for Small Satellite Applications
Olga Kondrateva, Grace Li Zhang, Julian Zobel +2
Small satellites used for Earth observation generate vast amounts of high-dimensional data, but their operation in low Earth orbit creates a significant communication bottleneck du…
HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis
Kangwei Xu, Bing Li, Grace Li Zhang +1
In high-level synthesis (HLS), C/C++ programs with synthesis directives are used to generate circuits for FPGA implementations. However, hardware-specific and platform-dependent ch…
VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
Zhuorui Zhao, Ruidi Qiu, Ing-Chao Lin +3
Large Language Models (LLMs) have demonstrated promising capabilities in generating Verilog code from module specifications. To improve the quality of such generated Verilog codes,…
Paradigm-Based Automatic HDL Code Generation Using LLMs
Wenhao Sun, Bing Li, Grace Li Zhang +3
While large language models (LLMs) have demonstrated the ability to generate hardware description language (HDL) code for digital circuits, they still face the hallucination proble…