22 citations · 96 across the 11 of their papers we have counts for
5 papers
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix)
Grace Li Zhang, Bing Li, Meng Li +5
With recent advances in reverse engineering, attackers can reconstruct a netlist to counterfeit chips by opening the die and scanning all layers of authentic chips. This relatively…
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning
Li Zhang, Bing Li, Jinglan Liu +2
At submicron manufacturing technology nodes, pro- cess variations affect circuit performance significantly. To counter these variations, engineers are reserving more timing margin…
PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model
Grace Li Zhang, Bing Li, Ulf Schlichtmann
In static timing analysis, clock-to-q delays of flip-flops are considered as constants. Setup times and hold times are characterized separately and also used as constants. The char…
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers
Grace Li Zhang, Bing Li, Ulf Schlichtmann
At nanometer manufacturing technology nodes, process variations significantly affect circuit performance. To combat them, post- silicon clock tuning buffers can be deployed to bala…
Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability
Grace Li Zhang, Bing Li, Ulf Schlichtmann
At submicron manufacturing technology nodes process variations affect circuit performance significantly. This trend leads to a large timing margin and thus overdesign to maintain y…