40 citations · 223 across the 19 of their papers we have counts for
13 papers · 1 filter
VirtualSync+: Timing Optimization with Virtual Synchronization
Grace Li Zhang, Bing Li, Xing Huang +4
In digital circuit designs, sequential components such as flip-flops are used to synchronize signal propagations. Logic computations are aligned at and thus isolated by flip-flop s…
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning
Li Zhang, Bing Li, Jinglan Liu +2
At submicron manufacturing technology nodes, pro- cess variations affect circuit performance significantly. To counter these variations, engineers are reserving more timing margin…
PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model
Grace Li Zhang, Bing Li, Ulf Schlichtmann
In static timing analysis, clock-to-q delays of flip-flops are considered as constants. Setup times and hold times are characterized separately and also used as constants. The char…
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers
Grace Li Zhang, Bing Li, Ulf Schlichtmann
At nanometer manufacturing technology nodes, process variations significantly affect circuit performance. To combat them, post- silicon clock tuning buffers can be deployed to bala…
Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability
Grace Li Zhang, Bing Li, Ulf Schlichtmann
At submicron manufacturing technology nodes process variations affect circuit performance significantly. This trend leads to a large timing margin and thus overdesign to maintain y…
Statistical Timing Analysis and Criticality Computation for Circuits with Post-Silicon Clock Tuning Elements
Bing Li, Ulf Schlichtmann
Post-silicon clock tuning elements are widely used in high-performance designs to mitigate the effects of process variations and aging. Located on clock paths to flip-flops, these…