27 citations · 31 across the 6 of their papers we have counts for
6 papers
Backing the Wrong Horse: How Bit-Level Netlist Augmentation can Counter Power Side Channel Attacks
Ali Asghar, Andreas Becher, Daniel Ziener
The dependence of power-consumption on the processed data is a known vulnerability of CMOS circuits, resulting in side channels which can be exploited by power-based side channel a…
Throughput Optimizations for FPGA-based Deep Neural Network Inference
Thorbjörn Posewsky, Daniel Ziener
Deep neural networks are an extremely successful and widely used technique for various pattern recognition and machine learning tasks. Due to power and resource constraints, these…
Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems
Daniel Ziener
In this treatise, my research on methods to improve efficiency, reliability, and security of reconfigurable hardware systems, i.e., FPGAs, through partial dynamic reconfiguration i…
Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning
Bernhard Schmidt, Daniel Ziener, Jürgen Teich +1
Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loo…
Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015)
Frank Hannig, Dirk Koch, Daniel Ziener
This volume contains the papers accepted at the Second International Workshop on FPGAs for Software Programmers (FSP 2015), held in London, United Kingdom, September 1st, 2015. FSP…
Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014)
Frank Hannig, Dirk Koch, Daniel Ziener
This volume contains the papers accepted at the First International Workshop on FPGAs for Software Programmers (FSP 2014), held in Munich, Germany, September 1st, 2014. FSP 2014 wa…