442 citations · 1.1k across the 16 of their papers we have counts for
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A 237 Gbps Unrolled Hardware Polar Decoder
Pascal Giard, Gabi Sarkis, Claude Thibeault +1
In this letter we present a new architecture for a polar decoder using a reduced complexity successive cancellation decoding algorithm. This novel fully-unrolled, deeply-pipelined…
On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations
Fatima Zahra Tazi, Claude Thibeault, Yvon Savaria +2
Experimental means to characterize delay faults induced by bit flips and SEUs in I/O blocks of SRAM-based FPGAs are proposed. A delay fault up to 6.2ns sensitized by an events chai…
Increasing the Speed of Polar List Decoders
Gabi Sarkis, Pascal Giard, Alexander Vardy +2
In this work, we present a simplified successive cancellation list decoder that uses a Chase-like decoding process to achieve a six time improvement in speed compared to successive…