Performance of a spin-based insulated gate field effect transistor

Abstract

Fundamental physical properties limiting the performance of spin field effect transistors are compared to those of ordinary (charge-based) field effect transistors. Instead of raising and lowering a barrier to current flow these spin transistors use static spin-selective barriers and gate control of spin relaxation. The different origins of transistor action lead to distinct size dependences of the power dissipation in these transistors and permit sufficiently small spin-based transistors to surpass the performance of charge-based transistors at room temperature or above. This includes lower threshold voltages, smaller gate capacitances, reduced gate switching energies and smaller source-drain leakage currents.

4 pages including 3 figures, APL in press

Cited by in corpus (7)

• Semiconductors between spin-polarized source and drain
• Electron Spin for Classical Information Processing: A Brief Survey of Spin-Based Logic Devices, Gates and Circuits
• Epitaxial ferromagnetic Fe${}_3$Si/Si(111) structures with high-quality hetero-interfaces
• AC magnetization transport and power absorption in non-itinerant spin chains
• Spin-orbit interaction and spin relaxation in a two-dimensional electron gas
• Analysis of electric-field-induced spin splitting in wide modulation-doped quantum wells
• A Digital Switch and Femto-Tesla Magnetic Field Sensor Based on Fano Resonance in a Spin Field Effect Transistor