Gate-defined quantum dot and charge noise analysis in a Forksheet transistor

Abstract

We report the cryogenic characterization of a 14-nm nMOS Forksheet transistor down to 10 mK. We demonstrate that the device retains transistor operation with improved characteristics at cryogenic temperatures, while also forming a gate-defined quantum dot that can be tuned to the single-electron regime. In the quantum-dot regime, we perform low-frequency charge-noise measurements across different charge occupations and observe an average charge-noise amplitude of $⟨S_0⟩=10\mu \mathrm{eV}/\sqrt{\mathrm{Hz}}$ at 1 Hz, with a minimum measured value of $3.3\mu \mathrm{eV}/\sqrt{\mathrm{Hz}}$. These results highlight the potential of Forksheet technology for the monolithic cointegration of quantum and classical CMOS functionalities in future quantum processors.

arXiv comment4 pages, 5 figures