Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement
arXiv:2606.19387
The paper presents a framework that uses large language models together with formal transformation rules to iteratively refine a design specification into correct register-transfer level (RTL) hardware code, aiming to make LLM‑generated hardware both interpretable and verifiable.
Abstract
Large language models (LLMs) have achieved remarkable success in software development. However, they are susceptible to hallucinations, meaning that they can introduce subtle semantic and logical errors. Due to the high stakes in chip design and manufacturing, hardware engineers are still reluctant to rely on LLMs for register-transfer level (RTL) generation. In this paper, we propose a hardware generation framework that combines the creativity and broad knowledge of LLMs with the explainability and mathematical rigor of formal methods. Specifically, we devise a set of transformation rules that cover various design decisions and hardware features. By iteratively applying these rules, an LLM agent can convert a design specification into an RTL program with guaranteed correctness. Experimental results demonstrate the effectiveness and efficiency of the framework.