Architecting Scalable Trapped Ion Quantum Computers using Surface Codes

Abstract

Trapped ion (TI) qubits are a leading quantum computing platform. Current TI systems have less than 60 qubits, but a modular architecture known as the Quantum Charge-Coupled Device (QCCD) is a promising path to scale up devices. There is a large gap between the error rates of near-term systems ($10^{-3}$ to $10^{-4}$) and the requirements of practical applications (below $10^{-9}$). To bridge this gap, we require Quantum Error Correction (QEC) to build logical qubits that are composed of multiple physical qubits. While logical qubits have been demonstrated on TI qubits, these demonstrations are restricted to small codes and systems. There is no clarity on how QCCD systems should be designed to implement practical-scale QEC. This paper studies how surface codes, a standard QEC scheme, can be implemented efficiently on QCCD-based systems. To examine how architectural parameters of a QCCD system can be tuned for surface codes, we develop a near-optimal topology-aware compilation method that outperforms existing QCCD compilers by an average of 3.8X in terms of logical clock speed. We use this compiler to examine how hardware trap capacity, connectivity and electrode wiring choices can be optimised for surface code implementation. In particular, we demonstrate that small traps of two ions are surprisingly ideal from both a performance-optimal and hardware-efficiency standpoint. This result runs counter to prior intuition that larger traps (20-30 ions) would be preferable, and has the potential to inform design choices for upcoming systems.

Submitted for review on March 12th 2025; Published in ASPLOS 2026, March 22-26; 15 pages, 13 figures

References in corpus (18)

• Large Scale Modular Quantum Computer Architecture with Atomic Memory and Photonic Interconnects
• Demonstration of the trapped-ion quantum-CCD computer architecture
• t$|$ket$⟩$ : A Retargetable Compiler for NISQ Devices
• Stim: a fast stabilizer circuit simulator
• A Race Track Trapped-Ion Quantum Processor
• Blueprint for a microwave trapped-ion quantum computer
• Coherent Diabatic Ion Transport and Separation in a Multi-Zone Trap Array
• Controlling fast transport of cold trapped ions
• Parallel Entangling Operations on a Universal Ion Trap Quantum Computer
• Benchmarking a trapped-ion quantum computer with 30 qubits
• How to wire a 1000-qubit trapped ion quantum computer
• Transversality and lattice surgery: exploring realistic routes towards coupled logical qubits with trapped-ion quantum processors
• Entangling an arbitrary pair of qubits in a long ion crystal
• A real-time, scalable, fast and highly resource efficient decoder for a quantum computer
• Transport of multispecies ion crystals through a junction in an RF Paul trap
• Muzzle the Shuttle: Efficient Compilation for Multi-Trap Trapped-Ion Quantum Computers
• TISCC: A Surface Code Compiler and Resource Estimator for Trapped-Ion Processors
• Demonstration of two-dimensional connectivity for a scalable error-corrected ion-trap quantum processor architecture