A real-time, scalable, fast and highly resource efficient decoder for a quantum computer

Abstract

To unleash the potential of quantum computers, noise effects on qubits' performance must be carefully managed. The decoders responsible for diagnosing noise-induced computational errors must use resources efficiently to enable scaling to large qubit counts and cryogenic operation. Additionally, they must operate at speed, to avoid an exponential slowdown in the logical clock rate of the quantum computer. To overcome such challenges, we introduce the Collision Clustering decoder and implement it on FPGA and ASIC hardware. We simulate logical memory experiments using the leading quantum error correction scheme, the surface code, and demonstrate MHz decoding speed - matching the requirements of fast-operating modalities such as superconducting qubits - up to an 881 and 1057 qubits surface code with the FPGA and ASIC, respectively. The ASIC design occupies 0.06 mm${}^2$ and consumes only 8 mW of power. Our decoder is both highly performant and resource efficient, unlocking a viable path to practically realising fault-tolerant quantum computers.

13 pages, 7 figures

References in corpus (12)

• Topological quantum memory
• Quantum Error Correction for Quantum Memories
• Quantum Computing with Very Noisy Devices
• Suppressing quantum errors by scaling a surface code logical qubit
• High threshold universal quantum computation on the surface code
• A Game of Surface Codes: Large-Scale Quantum Computing with Lattice Surgery
• Stim: a fast stabilizer circuit simulator
• Demonstration of fault-tolerant universal quantum gate operations
• Logical-qubit operations in an error-detecting surface code
• Neural-Network Decoders for Quantum Error Correction using Surface Codes:A Space Exploration of the Hardware Cost-Performance Trade-Offs
• Parallel window decoding enables scalable fault tolerant quantum computation
• Demonstration of logical qubits and repeated error correction with better-than-physical error rates

Cited by in corpus (11)

• Bridging Paradigms: Designing for HPC-Quantum Convergence
• Data-driven decoding of quantum error correcting codes using graph neural networks
• Resource Analysis of Low-Overhead Transversal Architectures for Reconfigurable Atom Arrays
• Distributed-HISQ: A Distributed Quantum Control Architecture
• Optimal number of stabilizer measurement rounds in an idling surface code patch
• Architecting Scalable Trapped Ion Quantum Computers using Surface Codes
• Programming tools for Analogue Quantum Computing in the High-Performance Computing Context -- A Review
• Snowflake: A Distributed Streaming Decoder
• Neural Decoders for Universal Quantum Algorithms
• Measurement-and Feedback-Driven Non-Equilibrium Phase Transitions on a Quantum Processor
• Pinball: A Cryogenic Predecoder for Surface Code Decoding Under Circuit-Level Noise