Chip-to-chip photonic connectivity in multi-accelerator servers for ML
arXiv:2501.18169
Abstract
We present a rack-scale compute architecture for ML using multi-accelerator servers connected via chip-to-chip silicon photonic components. Our architecture achieves (1) multi-tenanted resource slicing without fragmentation, (2) 74% faster rack-scale collective communication, and (3) 1.7X speedup in end-to-end ML training throughput.
Accepted at OFC 2025, https://www.ofcconference.org/en-us/home/program-speakers/symposia/advanced-packaging-and-integrated-optics/