Effectiveness of the syndrome extraction circuit with flag qubits on IBM quantum hardware

Abstract

Large scale quantum circuits are required to exploit the advantages of quantum computers. Despite significant advancements in quantum hardware, scalability remains a challenge, with errors accumulating as more qubits and gates are added. To overcome this limitation, quantum error-correction codes have been introduced. Although the success of quantum error correction codes has been demonstrated on superconducting quantum processors and neutral atom-based systems, there have been no experimental reports of error suppression using flag qubits on a quantum processor. IBM's quantum hardware features a non-topological coupling map, and past developments of quantum error correction codes on this platform have primarily explored the use of flag qubits. Here, we report the successful implementation of a syndrome extraction circuit with flag qubits on IBM quantum computers. Moreover, we demonstrate its effectiveness by considering the repetition code as a test code among the quantum error-correcting codes. Even though the data qubit is not adjacent to the syndrome qubit, logical error rates diminish as the distance of the repetition code increases from three to nine. Even when two flag qubits exist between the data and syndrome qubits, the logical error rates decrease as the distance increases similarly. This confirms the successful implementation of the syndrome extraction circuit with flag qubits on the IBM quantum computer.

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