Sub-5-nm Ultra-thin In$_2$O$_3$ Transistors for High-Performance and Low-Power Electronic Applications

Linqiang Xu; Lianqiang Xu; Jun Lan; Yida Li; Qiuhui Li; Aili Wang; Ying Guo; Yee Sin Ang; Ruge Quhe; Jing Lu

paper

Sub-5-nm Ultra-thin In $_{2}$ O $_{3}$ Transistors for High-Performance and Low-Power Electronic Applications

arXiv:2311.02943

Abstract

Ultra-thin (UT) oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, UT indium oxide (In $_{2}$ O $_{3}$ ) field-effect transistors (FETs) with thicknesses down to 0.4 nm exhibits extremely high drain current (10000 $μ$ A/ $μ$ m) and transconductance (4000 $μ$ S/ $μ$ m). Here, we employ the ab initio quantum transport simulation to investigate the performance limit of sub-5-nm gate length (Lg) UT In $_{2}$ O $_{3}$ FET. Based on the International Technology Roadmap for Semiconductors (ITRS) criteria for high-performance (HP) devices, the scaling limit of UT In $_{2}$ O $_{3}$ FETs can reach 2 nm in terms of on-state current, delay time, and power dissipation. The wide bandgap nature of UT In $_{2}$ O $_{3}$ (3.15 eV) renders it a suitable candidate for ITRS low-power (LP) electronics with Lg down to 3 nm. Both the HP and LP UT In $_{2}$ O $_{3}$ FETs exhibit superior energy-delay products as compared to other common 2D semiconductors such as monolayer MoS2 and MoTe2. Our study unveils the immense promise of UT In $_{2}$ O $_{3}$ for both HP and LP device applications.

16 pages, 7 figures

Sub-5-nm Ultra-thin In2​O3​ Transistors for High-Performance and Low-Power Electronic Applications

Abstract

Sub-5-nm Ultra-thin In $_{2}$ O $_{3}$ Transistors for High-Performance and Low-Power Electronic Applications