Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies

Abstract

The field of neuromorphic computing has been rapidly evolving in recent years, with an increasing focus on hardware design and reliability. This special session paper provides an overview of the recent developments in neuromorphic computing, focusing on hardware design and reliability. We first review the traditional CMOS-based approaches to neuromorphic hardware design and identify the challenges related to scalability, latency, and power consumption. We then investigate alternative approaches based on emerging technologies, specifically integrated photonics approaches within the NEUROPULS project. Finally, we examine the impact of device variability and aging on the reliability of neuromorphic hardware and present techniques for mitigating these effects. This review is intended to serve as a valuable resource for researchers and practitioners in neuromorphic computing.

10 pages, 4 figures, 4 tables

References in corpus (10)

• Deep Learning with Coherent Nanophotonic Circuits
• Parallel convolution processing using an integrated photonic tensor core
• Optoelectronic Reservoir Computing
• SLAYER: Spike Layer Error Reassignment in Time
• A silicon photonic modulator neuron
• A 0.086-mm${}^2$ 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS
• The Heidelberg spiking datasets for the systematic evaluation of spiking neural networks
• Ultra Low-Power and Real-time ECG Classification Based on STDP and R-STDP Neural Networks for Wearable Devices
• Spiker: an FPGA-optimized Hardware acceleration for Spiking Neural Networks
• DeepLaser: Practical Fault Attack on Deep Neural Networks

Cited by in corpus (2)

• Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge
• Emergent self-adaptation in an integrated photonic neural network for backpropagation-free learning