First Test Results of the Trans-Impedance Amplifier Stage of the Ultra-fast HPSoC ASIC

Abstract

We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end with \b{eta}-particles impinging on 3x3 AC-LGAD arrays (500 um pitch, 200x200 um2 metal) confirms a fast output rise time of 600 ps and good timing performance with a jitter of 45 ps. Further calibration experiments and TCT laser studies indicate some gain limitations that are being investigated and are driving the design of the second-generation pre-amplification stages to reach a jitter of 15 ps.

arXiv comment7 pages, 6 figures

References in corpus (5)

• Beam test results of a 16 ps timing system based on ultra-fast silicon detectors
• Resistive AC-Coupled Silicon Detectors: principles of operation and first results from a combined analysis of beam test and laser data
• First demonstration of 200, 100, and 50 um pitch Resistive AC-Coupled Silicon Detectors (RSD) with 100% fill-factor for 4D particle tracking
• PIONEER: Studies of Rare Pion Decays
• Potential for Improved Time Resolution Using Very Thin Ultra-Fast Silicon Detectors (UFSDs)