High-Throughput VLSI architecture for Soft-Decision decoding with ORBGRAND
arXiv:2105.07115 · doi:10.1109/ICASSP39728.2021.9414908
Abstract
Guessing Random Additive Noise Decoding (GRAND) is a recently proposed approximate Maximum Likelihood (ML) decoding technique that can decode any linear error-correcting block code. Ordered Reliability Bits GRAND (ORBGRAND) is a powerful variant of GRAND, which outperforms the original GRAND technique by generating error patterns in a specific order. Moreover, their simplicity at the algorithm level renders GRAND family a desirable candidate for applications that demand very high throughput. This work reports the first-ever hardware architecture for ORBGRAND, which achieves an average throughput of up to Gbps for a code length of at an SNR of dB. Moreover, the proposed hardware can be used to decode any code provided the length and rate constraints. Compared to the state-of-the-art fast dynamic successive cancellation flip decoder (Fast-DSCF) using a 5G polar code, the proposed VLSI implementation has more average throughput while maintaining similar decoding performance.
Please note that a mislabeling in Fig. 1 has occurred in the IEEE Xplore version of this paper. This error has been corrected in this version of the manuscript. (Accepted in ICASSP 2021)