Fault-tolerant Quantum Error Correction on Near-term Quantum Processors using Flag and Bridge Qubits

Abstract

Fault-tolerant (FT) computation by using quantum error correction (QEC) is essential for realizing large-scale quantum algorithms. Devices are expected to have enough qubits to demonstrate aspects of fault tolerance in the near future. However, these near-term quantum processors will only contain a small amount of noisy qubits and allow limited qubit connectivity. Fault-tolerant schemes that not only have low qubit overhead but also comply with geometrical interaction constraints are therefore necessary. In this work, we combine flag fault tolerance with quantum circuit mapping, to enable an efficient flag-bridge approach to implement FT QEC on near-term devices. We further show an example of performing the Steane code error correction on two current superconducting processors and numerically analyze their performance with circuit level noise. The simulation results show that the QEC circuits that measure more stabilisers in parallel have lower logical error rates. We also observe that the Steane code can outperform the distance-3 surface code using flag-bridge error correction. In addition, we foresee potential applications of the flag-bridge approach such as FT computation using lattice surgery and code deformation techniques.

arXiv comment11 pages, 14 figures, comments are most welcome

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• Efficient Magic State Distillation by Zero-Level Distillation
• Achieving fault tolerance on capped color codes with few ancillas
• Fault-tolerant quantum error correction using error weight parities
• Parallel syndrome extraction with shared flag qubits for Calderbank-Shor-Steane codes of distance three
• Low-Depth Flag-Style Syndrome Extraction for Small Quantum Error-Correction Codes
• Lightcone Bounds for Quantum Circuit Mapping via Uncomplexity
• QECV: Quantum Error Correction Verification
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• Testing of flag-based fault-tolerance on IBM quantum devices